Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders

A delay-insensitivity verification method is proposed for bit-level pipelined systolic dual-rail threshold logic adders, which achieve speed-up through early and input-incomplete carry output generation and which employ bit-wise completion at pipeline registers. The proposed method simplifies the verification task significantly, regardless of the operand length of the adder, such that analysis of three adjacent systoles for the eight possible early/late carry output generation scenarios is sufficient for detecting the input combinations which violate delay insensitivity. Using this method, structural modifications for re-establishing delay-insensitivity could be devised without sacrificing the speed-up advantages due to early carry generation. The method could also be applied to other pipelined data processing applications in dual-rail threshold logic.